Double sided versions of several power transistor types are devices that are already known in the literature e.g. bidirectional double sided Silicon Carbide IGBTs as illustrated in FIG. 43, Thyristors and Triacs. Almost any vertical-power high voltage devices are capable of bidirectionality by forming control features of such a device on both the front and back surfaces and sharing a common drift region of lowly doped silicon between the two sides of silicon.
Devices built in this configuration are generally required to have a separate driver circuit to control the front and rear control electrodes and provide the gate or base voltage and/or currents for the power switch. This is because there may be of the order of 1000V potential-difference between the frontside and rearside potentials when the transistor is in the off condition—and a single integrated circuit cannot generally sustain this within a single package.
One double-side bidirectional device is described in granted U.S. Pat. No. 9,054,706 (referred to as the ‘BTRAN’ herein and reproduced in FIG. 42 for convenience) and in its preferred embodiment is constructed in an NPN format using a P-type wafer with N+ emitter diffusions front and back sides. The NPN configuration is preferred in this case to benefit from electron conduction for the main power path between the emitters which is 2× higher conductivity than hole conduction as would be present for a PNP version
However, problems arising when using a P-type wafer include 1) Lack of suitable high-voltage P-type wafer: Only an N-type wafer can benefit from the NTD (Neutron Transmutation Doping) system that converts silicon into phosphorus at a uniform concentration giving excellent uniformity which supports >3 kV operation. 2) While in theory, there should be no problem producing a good quality P-type high voltage float-zone wafer for <3 kV operation, in practice these are not readily available because no market currently exists for them. 3) P-type wafers require different field termination structures and/or passivation requiring some development effort. 4) NPN devices constructed on P-wafers have an enhanced avalanche breakdown multiplication coefficient potentially reducing breakdown voltage. 5) For Silicon-Carbide devices, there is no known method of controlling the P-type dopants to the accuracy required for high voltage P-type wafers.
Alternatively, a PNP version of the BTRAN can be envisaged using an N-type wafer where the structure remains the same but the doping types are swapped (P→N and N→P). Unfortunately a PNP type power structure uses holes as its main carries for current and therefore has a 2:1 reduction in conductivity in the saturation resistance region vs NPN. Also, in the context of Silicon Carbide, the even more severe reduction of hole mobility in this material makes a PNP a poor choice.